This invention relates generally to analysis of circuit designs, and more particularly to manipulation of traces generated for a circuit design.
As the complexity in circuit design has increased, there has been a corresponding improvement in various kinds of verification and debugging techniques. In fact, these verification and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation, and formal verification.
During some of these verification techniques, a circuit design may be tested against a large set of properties to evaluate the operation of the circuit design. Properties are logical statements that describe some aspect of the circuit design. As the circuit design changes, the properties must be checked for consistency and re-written to comply with the design changes. Testing of the circuit design against a property may result in the generation of a number of traces that describe the activity or state of the circuit. For example, a trace may display a hi or low logical value of a clock, hex value of a register, indicate a change in value within a register, or other data about the circuit. These traces are often inspected in a viewer to verify and debug operation of the circuit.
Traditionally a viewer for debugging a circuit design consists of two columns, a first displaying a list of signals, and a second displaying the traces corresponding to the signals. Each signal is aligned with the associated trace in the same row, with vertical scrolls of the two columns being synchronized. The second column displaying the traces often has a zoom function, allowing the user to adjust the time scale on the horizontal axis amongst all the signals within the viewer.
The figures depict various embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein.